/*
 * Copyright (C) 2015 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-06-09 10:08:26
 *
 */


#ifndef ANLG_PHY_G1_H
#define ANLG_PHY_G1_H

#define CTL_BASE_ANLG_PHY_G1 0x403C0000


#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPIO_CLK_CTRL        ( CTL_BASE_ANLG_PHY_G1 + 0x0008 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_CTRL0          ( CTL_BASE_ANLG_PHY_G1 + 0x000C )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_CTRL1          ( CTL_BASE_ANLG_PHY_G1 + 0x0010 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_CTRL2          ( CTL_BASE_ANLG_PHY_G1 + 0x0014 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_BIST_CTRL      ( CTL_BASE_ANLG_PHY_G1 + 0x0018 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_CTRL0           ( CTL_BASE_ANLG_PHY_G1 + 0x001C )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_CTRL1           ( CTL_BASE_ANLG_PHY_G1 + 0x0020 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_CTRL2           ( CTL_BASE_ANLG_PHY_G1 + 0x0024 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_BIST_CTRL       ( CTL_BASE_ANLG_PHY_G1 + 0x0028 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_CTRL0           ( CTL_BASE_ANLG_PHY_G1 + 0x002C )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_CTRL1           ( CTL_BASE_ANLG_PHY_G1 + 0x0030 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_CTRL2           ( CTL_BASE_ANLG_PHY_G1 + 0x0034 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_BIST_CTRL       ( CTL_BASE_ANLG_PHY_G1 + 0x0038 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_IPPLL_CTRL0          ( CTL_BASE_ANLG_PHY_G1 + 0x003C )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_IPPLL_CTRL1          ( CTL_BASE_ANLG_PHY_G1 + 0x0040 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_IPPLL_CTRL2          ( CTL_BASE_ANLG_PHY_G1 + 0x0044 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_IPPLL_BIST_CTRL      ( CTL_BASE_ANLG_PHY_G1 + 0x0048 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TEST_SSC_CTRL        ( CTL_BASE_ANLG_PHY_G1 + 0x004C )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_ANA_PLL_RSVD         ( CTL_BASE_ANLG_PHY_G1 + 0x0050 )
#define REG_ANLG_PHY_G1_ANALOG_PLL_TOP_ANA_PLL_DUMY         ( CTL_BASE_ANLG_PHY_G1 + 0x0054 )

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPIO_CLK_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPIO_CLK_IN_CTRL        BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPIO_CLK_OUT_CTRL(x)    (((x) & 0x7))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_CTRL0 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_N(x)              (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_IBIAS(x)          (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_LPF(x)            (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_SDM_EN            BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_MOD_EN            BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_DIV_S             BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_CTRL1 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_NINT(x)           (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_KINT(x)           (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_CTRL2 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_RESERVED(x)       (((x) & 0xFF) << 3)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_CK2DSI_EN         BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_CLKOUT_EN         BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_DIV1_EN           BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_BIST_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_BIST_EN           BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_BIST_CNT(x)       (((x) & 0xFFFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_CTRL0 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_N(x)               (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_IBIAS(x)           (((x) & 0x3) << 6)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_LPF(x)             (((x) & 0x7) << 3)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_SDM_EN             BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_MOD_EN             BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_DIV_S              BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_CTRL1 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_NINT(x)            (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_KINT(x)            (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_CTRL2 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_RESERVED(x)        (((x) & 0xFF) << 2)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_CLKOUT_EN          BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_DIV1_EN            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_BIST_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_BIST_EN            BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_BIST_CNT(x)        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_CTRL0 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_N(x)               (((x) & 0x7FF) << 9)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_IBIAS(x)           (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_LPF(x)             (((x) & 0x7) << 4)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_SDM_EN             BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_MOD_EN             BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_DIV_S              BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_REF_SEL            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_CTRL1 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_NINT(x)            (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_KINT(x)            (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_CTRL2 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_RESERVED(x)        (((x) & 0xFF) << 1)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_POSTDIV            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_BIST_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_BIST_EN            BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_BIST_CNT(x)        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_IPPLL_CTRL0 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_N(x)               (((x) & 0x7FF) << 9)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_IBIAS(x)           (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_LPF(x)             (((x) & 0x7) << 4)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_SDM_EN             BIT(3)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_MOD_EN             BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_DIV_S              BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_REF_SEL            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_IPPLL_CTRL1 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_NINT(x)            (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_KINT(x)            (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_IPPLL_CTRL2 */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_RESERVED(x)        (((x) & 0xFF) << 3)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_CLKOUT_EN          BIT(2)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_POSTDIV            BIT(1)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_DIV1_EN            BIT(0)

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_IPPLL_BIST_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_BIST_EN            BIT(16)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_BIST_CNT(x)        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_TEST_SSC_CTRL */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_TWPLL_SSC_CTRL(x)       (((x) & 0xFF) << 24)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_LPLL_SSC_CTRL(x)        (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_GPLL_SSC_CTRL(x)        (((x) & 0xFF) << 8)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_IPLL_SSC_CTRL(x)        (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_ANA_PLL_RSVD */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_ANALOG_PLL_RESERVED(x)  (((x) & 0xFF))

/* REG_ANLG_PHY_G1_ANALOG_PLL_TOP_ANA_PLL_DUMY */

#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_ANALOG_PLL_DUMY_IN(x)   (((x) & 0xFFFF) << 16)
#define BIT_ANLG_PHY_G1_ANALOG_PLL_TOP_ANALOG_PLL_DUMY_OUT(x)  (((x) & 0xFFFF))


#endif /* ANLG_PHY_G1_H */

